The present invention relates generally to a computer system with two or more banks of dynamic random access memory (DRAM) chips. More particularly, the invention concerns problems which may arise on a memory bus during system power-up. Still more particularly, the present invention relates to a system for preventing contention on the memory bus between conflicting data signals from two or more DRAM banks.
FIG. 1 is a block diagram of a conventional computer system 10 that comprises a microprocessor or central processing unit ("CPU") 5, a local bus 7 coupled to the CPU 5 and to a memory controller 8. A system memory 12 also is shown coupled to the memory controller 8 through a memory bus 11. Power for the CPU 5, memory controller 8 and memory 12 is provided by one or more power supply circuits, generally denoted as 13 in FIG. 1. The microprocessor 5 shown in FIG. 1 may comprise, for example, any of the INTEL 8086.RTM. family of microprocessors (or a compatible device), and the local bus 7 could comprise an 8086 style local bus. The CPU local bus 7 typically includes a set of data lines D[31:0], a set of address lines A[31:0], and a set of control lines (not shown specifically). Details regarding the various bus cycles and protocols of the CPU local bus 7 are not discussed in detail herein, as they are not required for an understanding of the present invention, and are well known by those in the art. CPU 5 and memory controller 8 may be contained on separate chips, or may be fabricated on a single integrated processor chip.
The memory controller 8 controls data transactions to system memory 12. Thus, all read and write cycles to memory 12 are transmitted to the memory controller 8. In response, the memory controller 8 addresses the desired elements in memory 12 and performs either a read or write to the selected address in memory based upon the status of a read/write control line (not shown specifically) in the memory bus 11.
The system memory 12 typically includes banks of dynamic random access memory (DRAM) circuits. Two DRAM banks are shown in FIG. 1 for purposes of illustration. Many computer systems available commercially can accept at least four DRAM banks. The DRAM connects to the memory controller 8 via the memory bus 11, comprised of memory address lines, memory data lines, and various control lines. The DRAM banks, according to normal convention, comprise the working memory of the CPU 5.
Because several DRAM banks connect to the memory bus 11 in a typical computer system, precautionary steps must be taken to prevent multiple devices from simultaneously driving signals on the memory bus 11. For example, and referring now to FIG. 2, if DRAM bank #1 attempted to drive a "1" on data line D0 of the memory bus 11 while DRAM bank #2 simultaneously attempted to drive a "0" on data line D0, problems obviously would arise with bus contention, as two different signals were driven on the same line at substantially the same time.
To prevent the problem with bus contention, each DRAM bank typically includes a tri-state buffer 13 for each of its various data output lines. As will be understood by one skilled in the art, the tri-state buffer 13 is capable of driving both a low and a high output signal onto the memory bus 11, to indicate a digital "0" and a digital "1" when the output is enabled by the driver enable output from the DRAM. When the buffer 13 is not enabled, the tri-state buffer 13 functions to "disconnect" the data output line from the memory bus 11, so that neither a low or high signal is driven on the bus, and instead, the buffer presents a high impedence state thereby allowing other circuitry to determine the state of the bus. It should be noted that while FIG. 2 depicts four data lines, most conventional computer systems have at least thirty-two data lines in the memory bus 11, each of which would connect to the DRAM circuits through tri-state buffers.
An example of a conventional tri-state buffer is shown in FIG. 3. In accordance with conventional techniques, the tri-state buffer 13 receives an input signal x, and produces an output signal y, which is driven onto the associated bus line. The tri-state buffer 13 also receives an active low (or high) enable signal. If the enable signal is asserted, then the output signal y is the same as the input signal x. If, conversely, the enable signal is deasserted, then a high impedance state appears on the output of the buffer 13.
Referring again to FIG. 1, data generally is transferred between the DRAM banks and the memory controller 8 in two steps. First, the controller 8 generates signals on the address lines of the memory bus 11 representing the row address of the desired memory location, which are latched into the memory 12 when a row address strobe: (RAS) signal is asserted low by the controller 8. At the next, or at subsequent clock cycles, the memory 12 latches in the column address when a column address strobe (CAS) signal is asserted low by the memory controller 8. During a write transaction, data is latched into memory 12 on the falling edge of the CAS signal. In a read cycle, data from the selected memory cell is driven onto the data lines of the memory bus 11 shortly after the assertion of the CAS signal
This method of accessing multiple DRAM banks can cause problems during system power-up. After turning on the system, the power supply 13 does not instantaneously reach its nominal operating voltage level. Instead, the power supply ramps up to its operating voltage level. A certain period of time expires from turning on the power switch of the computer (or initiating reset), before the power supply outputs become stable. This time varies from system to system and among power supplies. During this stabilization period, devices in the computer system may began operating, or may even malfunction because of the low power conditions present during the stabilization period.
One of these devices that may malfunction or prematurely begin operation is the memory controller 8. If the memory controller 8 errantly begins performing memory transactions power-up, the DRAM banks may respond by driving data signals onto the memory bus. If two DRAM banks are addressed with memory read requests at substantially the same time during power-up, bus contention may occur, as two different DRAM banks attempt to drive out conflicting signals onto the same memory bus. As a result, the system may fail, the DRAM's may latch-up, and the life of the DRAM may be shortened.
Various attempts have been made in the prior art to prevent this problem. One proposed solution is to provide a voltage detection circuit in each DRAM bank, to disconnect the control signals (such as RAS or CAS) until a sufficient voltage threshold is achieved by the power supply. Another proposed solution is to provide an analog time delay circuit to disconnect the control signals until a certain minimum time period has elapsed after power-up. FIGS. 4A and 4B illustrate a prior art design which relies primarily on an analog time delay circuit to disable the receipt of a RAS (and/or CAS) control signal giving the power supply a minimum time period to reach a nominal operating level.
The time delay circuit of FIG. 4A connects to the power supply circuit 13 of FIG. 1 by means of the power pin to the DRAM (VCC). The time delay circuit provides a power up (Pwrup) signal (active high during power-up) when the power supply begins to ramp. Qa is initally on, but Qb is off because the substrate voltage Vbb is not yet pumped down. When Qb turns on it overpowers Qa which drives the first inverter high. Capacitor C.sub.1 provides an additional delay to the ramping up of the first inverter, causing Pwrup to stay high until C.sub.1 is charged. When Ca is charged, the output of the second invertor goes low, causing Pwrup to also go low.
The Pwrup signal, which is the output of the time delay circuit of FIG. 4A, is provided as an input signal to the RAS buffer circuit of FIG. 4B. When Pwrup goes low, indicating that the power supply has reached a threshold voltage, transistor Q.sub.6 turns off, permitting the RAS input signal to propagate to the output buffers.
The approach depicted in FIGS. 4A and 4B, therefore, implements a time delay component to delay operation until a capacitor C.sub.1 is charged. The circuit also reacts to the power supply ramp time because this affects the rate at which Vbb and C1 charge. The problem with this approach, however, is that the stabilization period for the power supply may vary considerably from one system to another. Consequently, the time delay period must be designed for "worst case" scenarios, and thus time is wasted in most systems. A DRAM designed to account for a worst case slow power supply ramp may not be ready when required in a system with a fast ramp power supply. This wasted time period may become especially noticeable in certain systems, such as in portable computers with power management features. The reliance on a long time delay to prevent DRAM latch-up, is at best an inefficient solution.